1-73 mt5c2568 883c austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000007 mt5c2568 883c 32k x 8 sram austin semiconductor, inc. available as military specifications ? smd 5962-88662 ? mil-std-883 features ? ultra high speed 12, 15ns ? high speed: 20, 25, 35 and 45ns ? battery backup: 2v data retention ? low power standby ? high-performance, low-power, cmos double-metal process ? single +5v ( 10%) power supply ? easy memory expansion with / c / e ? all inputs and outputs are ttl compatible options marking ? timing 12ns access (contact factory) -12 15ns access -15 20ns access -20 25ns access -25 35ns access -35 45ns access -45 55ns access -55* 70ns access -70* ? packages ceramic dip (300 mil) c no. 108 ceramic dip (600 mil) cw no. 110 ceramic lcc (28 leads) ec no. 204 ceramic lcc (32 leads) ecw no. 208 ceramic flat pack f no. 302 ceramic soj dcj no. 500 ? 2v data retention, low power standby l ? radiation tolerant (epi) e *electrical characteristics identical to those provided for the 45ns access devices. 32k x 8 sram pin assignment (top view) 28-pin lcc (c-11) 28-pin flat pack (f-12) general description the austin semiconductor sram family employs high- speed, low-power cmos designs using a four-transistor memory cell. austin semiconductor srams are fabricated using double-layer metal, double-layer polysilicon tech- nology. for flexibility in high-speed memory applications, aus- tin semiconductor offers chip enable ( / c / e) and output en- able ( ? o / e) capability. these enhancements can place the outputs in high-z for additional flexibility in system de- sign. writing to these devices is accomplished when write enable ( ? w / e) and / c / e inputs are both low. reading is accomplished when ? w / e remains high and / c / e and ? o / e go low. the device offers a reduced power standby mode when disabled. this allows system designs to achieve low standby power requirements. a6 a5 a4 a3 a2 a1 a0 nc dq1 a8 a9 a11 nc oe a10 ce dq8 dq7 a7 a12 a14 nc vcc we a13 dq2 dq3 vss nc dq4 dq5 dq6 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 4 3 2 1 32 31 30 14 15 16 17 18 19 20 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq1 dq2 dq3 vss vcc we a13 a8 a9 a11 oe a10 ce dq8 dq7 dq6 dq5 dq4 32-pin lcc (c-12) a6 a5 a4 a3 a2 a1 a0 dq1 dq2 a13 a8 a9 a11 oe a10 ce dq8 dq7 a7 a12 a14 vcc we dq3 vss dq4 dq5 dq6 4 5 6 7 8 9 10 11 12 26 25 24 23 22 21 20 19 18 13 14 15 16 17 3212827 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq1 dq2 dq3 vss vcc we a13 a8 a9 a11 oe a10 ce dq8 dq7 dq6 dq5 dq4 28-pin soj 28-pin dip (d15/d10) sram
1-74 mt5c2568 883c austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000007 mt5c2568 883c 32k x 8 sram austin semiconductor, inc. the l version provides an approximate 50 percent reduction in cmos standby current (i sbc 2 ) over the standard version. all devices operate from a single +5v power supply and all inputs and outputs are fully ttl compatible. functional block diagram a a a a a a a a vcc gnd a oe we ce column decoder 262,144-bit memory array i/o control (lsb) dq1 dq8 power down (lsb) aaaaaa row decoder truth table mode / o / e / c / e ? w / e dq power standby x h x high-z standby read l l h q active read h l h high-z active write x l l d active
1-75 mt5c2568 883c austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000007 mt5c2568 883c 32k x 8 sram austin semiconductor, inc. absolute maximum ratings* voltage on any input or dq relative to v ss .... -2v to +7v voltage on vcc supply relative to vss .............. -1v to +7v storage temperature ................................... -65 c to +150 c power dissipation ............................................................. 1w short circuit output current ..................................... 50ma lead temperature (soldering 10 seconds) .............. +260 c junction temperature ................................................ +175 c capacitance description conditions symbol min max units notes input capacitance t a = 25 c, f = 1mhz c i 8pf 4 output capacitance v cc = 5v c o 8pf 4 *stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indi- cated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. electrical characteristics and recommended dc operating conditions (-55 c t c 125 c; v cc = 5v 10%) description conditions symbol min max units notes input high (logic 1) voltage v ih 2.2 v cc +1.0 v 1 input low (logic 0) voltage v il -0.5 0.8 v 1, 2 input leakage current 0v v in v cc il i -5 5 m a output leakage current outputs disabled il o -5 5 m a 0v v out v cc output high voltage i oh = -4.0ma v oh 2.4 v 1 output low voltage i ol = 8.0ma v ol 0.4 v 1 description conditions symbol -12 -15 -20 -25 -35 -45 units notes power supply / c / e v il ; v cc = max current: operating f = max = 1/ t rc (min) i cc 190 165 150 140 135 130 ma 3 output open power supply / c / e 3 v ih ; v cc = max current: standby f = max = 1/ t rc (min) i sbt 1 60 50 45 40 40 40 ma output open / c / e 3 v ih , all other inputs v il or 3 v ih , v cc = max i sbt 2 25 25 25 25 25 25 ma f = 0 hz / c / e 3 v cc -0.2v; v cc = max v il v ss +0.2v i sbc 2 55 5555 ma v ih 3 v cc -0.2v; f = 0 hz l version only i sbc 2 44 4444 ma max
1-76 mt5c2568 883c austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000007 mt5c2568 883c 32k x 8 sram austin semiconductor, inc. electrical characteristics and recommended ac operating conditions (note 5) (-55 c t c 125 c; v cc = 5v 10%) -12 -15 -20 -25 -35 -45 sym min max min max min max min max min max min max units notes read cycle read cycle time t rc 12 15 20 25 35 45 ns address access time t aa 12 15 20 25 35 45 ns chip enable access time t ace 12 15 20 25 35 45 ns output hold from address change t oh22 2222ns enable to output in low-z t lzce 2 2 2222ns7 disable to output in high-z t hzce 7 8 9 10 14 15 ns 6, 7 chip enable to power-up time t pu00 0000ns4 chip disable to power-down time t pd 12 15 20 25 35 45 ns 4 output enable access time t aoe 6 8 9 10 14 15 ns output enable to output in low-z t lzoe 0 0 0000ns output disable to output in high-z t hzoe 4 6 8 10 14 15 ns 6 write cycle write cycle time t wc 12 15 20 25 35 45 ns chip enable to end of write t cw 10 12 15 18 20 25 ns address valid to end of write t aw 10 12 15 18 20 25 ns address setup time t as00 0000ns address hold from end of write t ah22 2222ns write pulse width t wp 10 12 15 17 20 25 ns data setup time t ds 6 7 10 12 15 20 ns data hold time t dh00 0000ns write disable to output in low-z t lzwe 2 2 2222ns7 write enable to output in high-z t hzwe 06 07 010 011014015ns6, 7 description
1-77 mt5c2568 883c austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000007 mt5c2568 883c 32k x 8 sram austin semiconductor, inc. low v cc data retention waveform ac test conditions input pulse levels ...................................... vss to 3v input rise and fall times ....................................... 5ns input timing reference level ............................... 1.5v output reference level ....................................... 1.5v output load ................................ see figures 1 and 2 q 255 480 5 pf +5v q 255 480 30 pf +5v fig. 1 output load fig. 2 output load equivalent equivalent don? care undefined data retention mode t cdr t r 4.5v 4.5v dr v dr v v v ih il ce vcc >2v data retention electrical characteristics (l version only) description conditions symbol min max units notes v cc for retention data v dr 2v data retention current / c / e 3 (v cc - 0.2v) v cc = 2v i ccdr 1.0 ma v in 3 (v cc - 0.2v) or 0.2v v cc = 3v 1.5 ma chip deselect to data t cdr 0 ns 4 retention time operation recovery time t r t rc ns 4, 11 notes 1. all voltages referenced to v ss (gnd). 2. -3v for pulse width < 20ns. 3. i cc is dependent on output loading and cycle rates. the specified value applies with the outputs 1 unloaded, and f = ????? hz. t rc (min) 4. this parameter is guaranteed but not tested. 5. test conditions as specified with the output loading as shown in fig. 1 unless otherwise noted. 6. t hzce, t hzoe and t hzwe are specified with cl = 5 pf as in fig. 2. transition is measured 500mv typical from steady state voltage, allowing for actual tester rc time constant. 7. at any given temperature and voltage condition, t hzce is less than t lzce and t hzwe is less than t lzwe. 8. ? w / e is high for read cycle. 9. device is continuously selected. chip enable and output enable are held in their active state. 10. address valid prior to or coincident with latest occurring chip enable. 11. t rc = read cycle time. 12. chip enable ( / c / e) and write enable ( ? w / e) can initiate and terminate a write cycle.
1-78 mt5c2568 883c austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000007 mt5c2568 883c 32k x 8 sram austin semiconductor, inc. read cycle no. 1 8, 9 read cycle no. 2 7, 8, 10 don? care undefined t rc t ace t lzce t aoe t lzoe t hzce t pu t pd high-z ce oe dq icc t hzoe data valid t rc t aa t oh valid previous data valid data valid addr q
1-79 mt5c2568 883c austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000007 mt5c2568 883c 32k x 8 sram austin semiconductor, inc. t wc t aw t cw t ah t as t wp t dh t ds high-z ce we addr d q data valid don? care undefined write cycle no. 2 7, 12 (write enable controlled) write cycle no. 1 12 (chip enable controlled) t wc t aw t as t cw t ah t wp ce we addr d high-z q t dh t ds data valid note: output enable ( / o / e) is inactive (high).
1-80 mt5c2568 883c austin semiconductor, inc., reserves the right to change products or specifications without notice. rev. 11/97 ds000007 mt5c2568 883c 32k x 8 sram austin semiconductor, inc. electrical test requirements subgroups mil-std-883 test requirements (per method 5005, table i) interim electrical (pre-burn-in) test parameters 2, 8a, 10 (method 5004) final electrical test parameters 1*, 2, 3, 7*, 8, 9, 10, 11 (method 5004) group a test requirements 1, 2, 3, 4**, 7, 8, 9, 10, 11 (method 5005) group c and d end-point electrical parameters 1, 2, 3, 7, 8, 9, 10, 11 (method 5005) * pda applies to subgroups 1 and 7. ** subgroup 4 shall be measured only for initial qualification and after process or design changes, which may affect input or output capacitance.
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